1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and a manufacturing method of the same. In particular, the present invention relates to a non-volatile semiconductor memory device having a floating gate, so as to carry out write-in and erasure of data by storing and releasing a charge in the floating gate, and relates to a manufacturing method of the same.
2. Description of the Related Art
Conventionally, a NOR type flash memory, as shown in the equivalent circuit diagram of FIG. 15, has been known as a non-volatile semiconductor device. In this flash memory, bit lines BL connected to the drains of memory cells MC and word lines WL for selecting a control gate of memory cells MC are wired so as to cross at right angles wherein memory cells MC are aligned in a matrix form. The sources of memory cells MC are connected to a common source line CSL so that all of the sources within the same block are shared.
In such a flash memory as shown in FIG. 16, control gates 11 (in the Y direction in FIG. 16) are aligned above active regions 10, which are aligned in a striped form (in the X direction in FIG. 16), so that the active regions 10 and the control gates 11 cross at right angles and floating gates (not shown) are arranged beneath the control gates 11 above the active regions 10 independently for every bit. In addition, the drains of memory cells MC are connected to bit lines BL via drain contacts 12 while word lines WL are wired parallel to the control gates 11 so that the word lines WL and the bit lines BL cross at right angles. On the other hand, diffusion wires 51 have been formed in such a manner that the diffusion wires 51 are self-aligned with the control gates 11 in the spaces between the control gates 11 on the source sides of the memory cells MC while the diffusion wires 51 are connected to metal wires in the upper layer via source contacts 50 placed in intervals ranging from several memory cells MC to several dozens of memory cells MC. A P+ diffusion layer 13 for supplying a potential to the P well (not shown) of the memory cell region, and an N+ diffusion layer 14 for supplying a potential to the N well (not shown), which is formed so as to surround the P well, are placed outside of the memory cell array and are connected to metal wires via contact plugs.
Memory cell array MCA of this flash memory is formed within a P well 18 which is formed within a silicon substrate 17 as shown in the cross sectional view of FIG. 17 where this P well 18 is surrounded by a deep N well 19b. A plurality of memory cells MC forms one block and each block is electrically isolated.
In a memory cell MC, a floating gate 25, an ONO film 26 and a control gate 11 are layered above a gate insulating film 24, formed on a P well 18 as shown in FIG. 18, where a source 27 and a drain 28 are formed of N+ diffusion layers which have been formed so as to be self-aligned with the control gate 11. In addition, sidewalls 29 are formed on the sides of the floating gate 25 and the control gate 11, that have been layered, of an insulating film in a self-aligned manner. Silicide layers 30 are formed on the source 27, the drain 28 and the control gate 11 in a self-aligned manner. The drain 28 of the memory cell MC is placed in such a manner that the drain 28 is shared by the adjacent cell and is connected to a bit line BL by means of a contact plug. The bit line BL is wired so that the bit line BL and the control gate 11 cross at right angles.
In addition, as shown in FIG. 19, each memory cell MC is isolated from the other cells by means of an isolation region 32 formed in a trench created in the surface of the silicon substrate 17. The floating gate 25 is placed on the gate insulating film 24 above active region 10 so that a portion of the floating gate 25 overlaps the isolation region 32. The floating gate 25 is surrounded by the ONO film 26 and the control gate 11 is placed above the floating gate 25.
Furthermore, as shown in FIG. 20, the oxide film of the isolation region 32 is removed from a space between control gates 11 on the source side so that common source line CSL formed of an N+ diffusion layer is wired parallel to the control gate 11. The common source line CSL is connected to a metal wire 53 via contact plugs 52 placed in intervals ranging from several memory cells to several dozens of memory cells and, thereby, the sources of all the memory cells are shared within the same block.
In such a flash memory, for example, the drain is set at 5V, the control gate is set at 10V, the source and the P well are set at 0V and, thereby, hot electrons that have been generated in the vicinity of the drain are injected into the floating gate so that data is written in.
In addition, for example, the control gate is set at −10V, the drain is opened, the source and the P well are set at 10V and, thereby, an FN tunnel current is allowed to flow from the floating gate to the source and channel region so that the data is erased.
Furthermore, a voltage of 5V is supplied to the gate, a voltage of 1V is supplied to the drain and a voltage of 0V is supplied to the source and P well and, thereby, the data is read out. The existence of data can be determined because a cell in the written-in condition has a high threshold value due to a charge being stored in the floating gate preventing a current from flowing while a cell in the erased condition allows a current to flow.
It is usually necessary in a flash memory to maintain a low resistance in the common source line in order to maintain a rapid random access time at the time of read out.
On the other hand, it is necessary to restrict the impurity concentration of the source and the diffusion of impurities caused by heat treatments so that the effective channel length is secured in order to prevent a short channel effect. Therefore, it has been difficult for a conditional flash memory to maintain a low resistance in the source as miniaturization of the device progresses.
Thus, a technique has been proposed wherein the common source line is formed of a diffusion layer having a low concentration and a silicide layer is formed on this diffusion layer in a self-aligned manner and, thereby, an increase in the source resistance can be restricted (for example, Japanese unexamined patent publication No. HEI 10 (1998)-74915).
However, the more miniaturization of the device progresses where the width of the common source line is reduced, the less an increase in the source resistance can be ignored and, therefore, a further reduction in the source resistance is required at the present condition.